This invention relates to methods for constructing a semiconductor device; and more particularly to methods for fabricating self-aligned electrodes on a semiconductor substrate as a portion of such a device. A variety of semiconductor devices require self-aligned electrodes as a portion of their overall structure. For example, charge coupled devices are comprised of hundreds of electrodes lying traversely to a charge transfer channel that is formed in a semiconductor substrate. Clocking signals are applied to the electrodes to form potential wells in the channel directly under the electrodes. These potential wells are utilized to propagate charge packets from one end of the channel to another. As another example, self-aligned electrodes comprise a portion of the storage cells within MOS random access memories. Typically within each cell, one electrode forms one plate of storage capacitor while a second electrode lies adjacent to the one electrode to form a gate between the storage capacitor and a bit line. Charge is transferred from the storage capacitor to the bit line by applying appropriate clocking signals to the gate electrode.
Over the last several years, the trend in the semiconductor industry has been to make these and other adjacent electrodes as small as possible. This for example, allows the charge coupled device to have more stages per chip; and allows the random access memory to have storage cells per chip. Typically, such electrodes have a minimum width of approximately 8 microns.
As the width of the electrodes is made small however, the task of aligning the electrodes with each other becomes more difficult. This is because the dimensions of the masks which are used to form the electrodes can only be controlled within certain tolerances; and because the masks that are used can also only be aligned with each other within certain tolerances. Typically, to overcome these tolerance problems, alternate ones of the electrodes are fabricated such that they slightly overlap the other electrodes. For example, an electrode having a width of 8 microns is typically overlapped on either side by 2 microns of the adjacent electrode. Such an overlap is necessary in order to avoid gaps between adjacent electrodes. These gaps would form potential barriers in the underlying substrate region which in turn would adversely affect the device's operation.
Unfortunately however, the overlap of the adjacent electrodes also produces an adverse effect. In particular, the overlap gives rise to an interelectrode capacitance. Typically, this capacitance is on the order of several thousand picofarads. As a result of this capacitance, the device's operation is slowed. That is, the rise and fall time of signals applied to the electrodes is limited in proportion to the amount of interelectrode's capacitance. Also, this interelectrode capacitance has the effect of increasing the power which the device dissipates. Specifically, the energy stored in the interelectrode capacitance is 1/2CV.sup.2 where C is the interelectrode capacitance and V is the voltage across the capacitance. This energy is dissipated and turned into heat each time the clocking signals applied to the electrodes switch from a high voltage level to a low voltage level. And this heat may adversely affect the operation of the device.
Accordingly, it is one object of the invention to provide an improved method of fabricating adjacent electrodes in a semiconductor device.
Another object of the invention is to provide a self-aligning method of fabricating adjacent electrodes on a semiconductor device.
Still another object of the invention is to provide a method of fabricating self-aligned electrodes on a semiconductor device by use of infrared photolithography.